1. Field of the Invention
The present invention relates to either discrete devices or integrated power semiconductor devices including MOS-gated power devices such as, for example, power MOSFETs, IGBTs, MOS-gated thyristors or other MOS-gated power devices. In particular, the invention relates to a MOS-gated power device having an improved gate resistance, an improved dynamic performance, and a higher frequency of operation.
2. Discussion of the Related Art
MOS-technology power devices are used for applications wherein high currents at high voltages are to be switched on and off in times on the order of hundreds of nanoseconds. There is therefore a need for MOS-technology devices capable of handling high power levels in short time periods. Thus, there is a need for MOS-technology power devices with suitable dynamic performance capability.
In addition, it is desirable to achieve large channel widths per unit area, and thus MOS-technology power devices are typically made up of a large number of elementary cells that are connected in parallel to form an array of elementary cells. This arrangement desirably yields a resistance for the channel region of the power device in an on-state (Ron) that can be relatively low.
U.S. Pat. No. 4,593,302 (Lidow et al) discloses a high power MOSFET including a plurality of elementary cells formed from a plurality of polygonal regions (base regions) in a semiconductor material layer, which have a square or hexagonal shape. Each polygonal region is surrounded by a narrow conduction region of enhanced conductivity N.sup.+ that is disposed beneath a gate oxide layer. Each of the polygonal regions includes an opposite conductivity ring region (source region) respectively. The ring regions together with the polygonal regions and the conductive region define channel regions of the high power MOSFET device. The gate oxide layer includes polygonal shaped openings immediately above the polygonal regions which expose the source rings. A polysilicon gate electrode made up of a polysilicon layer is disposed over the gate oxide layer. A silicon dioxide layer is deposited atop the polysilicon layer and insulates the polysilicon gate electrode from a source electrode, which is subsequently deposited over an entire upper surface of the semiconductor wafer. A drain electrode is disposed at a bottom surface of the semiconductor wafer. In addition, a boundary region is disposed in the semiconductor material layer and surrounds the array of elementary cells in order to provide an edge structure that increases a breakdown voltage of the high power MOSFET.
Thus, Lidow et al discloses a plurality of base regions that are spaced from one another and that in a preferred embodiment are hexagonal in shape. In addition, Lidow et al discloses that the plurality of the spaced base regions are spaced from each other by a body of semiconductor material which is the drain region of the high power MOSFET and is a continuous mesh. Further, Lidow et al discloses that the conductive channel regions are defined by the outer periphery of the source regions and the periphery of the spaced base regions. In particular, Lidow et al discloses that the channel region around the periphery of the spaced base regions results in a carrier flow path that is outward from the source regions toward an adjacent base region and downward into the common drain region.
The dynamic performance of cellular MOS-technology power device according to the related art is however limited by a presence of parasitic capacitances and by a gate resistance of the device. These problems are exacerbated by interruptions in the array of elementary cells, which are provided for essentially three reasons. First, in order to reduce the gate resistance of the power device, metal gate fingers are provided over an outer surface of an area containing a plurality of the polygonal regions and the metal gate fingers make contact to the polysilicon gate layer in order to keep the polysilicon gate layer at substantially a same potential. Second, the metal gate fingers are interrupted in regions of the chip where a source electrode is provided and in an area where a source bond pad is provided for bonding to the source electrode. Third, the metal gate fingers are interrupted in regions of the chip where a gate bond pad is provided. These interruptions introduce asymmetries within the power MOSFET device resulting in points of low breakdown or undesirable performance in of the power device. In particular, the metal gate fingers interrupting the array of elementary cells result in the structure having a non-uniform distance between adjacent polygonal regions across the active area of the power device chip. Also, since a total number of the metal gate fingers contacting the polysilicon gate layer is limited, the distributed gate resistance can be very non-uniform. For example, the elementary cells near the metal gate fingers experience a significantly lower gate resistance than those further away from the metal gate fingers.
In view of the related art described, it is an object of the present invention to provide an improved MOS-technology power device integrated structure.